The present invention relates to a method for fabricating a semiconductor device, and more particularly, to an etching method using a hard mask in a semiconductor device.
For a gate formation in a semiconductor device fabrication process, as a pattern size has been reduced, a loss of a gate hard mask nitride layer has been increased during performing a gate etching method and a landing plug contact etching method. A height of a gate hard mask nitride layer which is finally remaining after etching the landing plug contact to prevent a self aligned contact (SAC) fail has been increased, and a deposition thickness of the gate hard mask nitride layer has been increased as well. Accordingly, it is difficult to obtain a vertical cross-sectional profile since the deposition thickness of the gate hard mask nitride layer is large during etching the gate hard mask nitride layer. Also, a bowing phenomenon or a sloped profile may be obtained and thus, gate critical dimension uniformity within a wafer may be degraded due to the bowing phenomenon for each location of the wafer or the different slope angles.
As for etching a gate electrode formed of polysilicon and tungsten, a photoresist layer formed over the gate hard mask nitride layer and serving as an etch barrier is removed. Then, the gate electrode is etched using the gate hard mask nitride layer as an etch barrier. Due to the use of the gate hard mask layer as the etch barrier, a polymer generated during the etching of the gate hard mask nitride layer may be removed, thereby removing un-etch or residues generated during etching a gate metal.
However, in the case of etching the gate electrode formed of tungsten using the gate hard mask nitride layer as the etch barrier, a fluorine-based etch gas is used. In this case, since an etch selectivity of the fluorine-based etch gas is low to the gate hard mask nitride layer, a large loss may be generated on the gate hard mask nitride layer. Accordingly, it is necessary to increase an initial deposition thickness of the gate hard mask nitride layer.
FIG. 1A illustrates a slope profile of a typical gate hard mask pattern, and FIG. 1B illustrates a loss on a typical gate hard mask pattern generated during etching a gate electrode. As shown in FIGS. 1A and 1B, a gate insulation layer 12 is formed over a substrate 11, and a gate electrode layer 13 is formed over the gate insulation layer 12. A gate hard mask pattern 14 is formed over the gate electrode 13. The gate hard mask pattern 14 includes a nitride layer. Then, a gate etching process is performed to form a patterned gate electrode 13A.
An etch profile of the gate pattern 14 has a slope as shown in FIG. 1A. A loss is generated on the gate hard mask pattern 14 during the gate etching process as shown in FIG. 1B. A remaining gate hard mask pattern after the gate etching process is identified with a reference numeral 14A. Limitations shown in FIGS. 1A and 1B may be generated at a bit line etching process using a hard mask (e.g., a bit line hard mask nitride layer) as well.